1. Field of the Invention
The present invention relates generally to an input protective apparatus for a semiconductor device implementing MOS transistors, and more particularly toward protective circuitry capable of protecting input MOS transistors of the device from effects of noise signals having different current and frequency characteristics.
FIG. 1 is a plan view showing a conventional semiconductor integrated circuit having input protective circuits arranged, and FIG. 2 is an electric circuit diagram showing a conventional input protective circuit.
In FIG. 1, a semiconductor integrated circuit 1 is provided with terminals 11 to 1n connected to external circuits. Input protective circuits 31 to 3n are arranged between the terminals 11 to 1n and internal circuits 41 to 4n. As shown in FIG. 2, the input protective circuit 31 comprises an N channel MOS transistor Q1, a resistor element R2 and an N channel MOS transistor Q2. The transistor Q1 has a drain connected to the terminal 11 at a node N1, and a source connected to a ground. In addition, the N channel MOS transistor Q1 has a gate connected to the terminal 11 at a node N2.
Furthermore, one end of the resistor element R2 is connected to the node N2 and the other end thereof is connected to a node N3. The N channel MOS transistor Q2 has a drain connected to the node N3. In addition, an N channel MOS transistor Q3 in the internal circuit 41 to be protected has a gate connected to the node N3. The N channel MOS transistor Q2 has a source and a gate connected to a ground, respectively. The N channel MOS transistor Q1 includes, for example, a so-called field oxide transistor obtained by selectively oxidizing a region between active layers serving as a source and a drain.
FIG. 3 is a diagram showing a cross-sectional structure of the field oxide transistor, and FIG. 4 is a diagram for explaining a punch-through phenomenon in the conventional input protective circuit.
The field oxide transistor shown in FIG. 3 is generally used as the MOS transistor Q1 having a thick gate insulating film shown in FIG. 2. In FIG. 3, active regions 21 and 22 formed of an N+ diffusion layer are formed on a P type semiconductor substrate 28, the active region 21 serving as a source and the active region 22 serving as a drain. In order to separate the active regions 21 and 22, a thick oxide film 23 is selectively formed therebetween. An insulating layer 24 is formed on the oxide film 23 and the active regions 21 and 22. A metal interconnection 25 is formed on the insulating layer 24. In FIG. 3, since an electrode formed of a metal interconnection 26 is formed on the source region which is the active region 21 separated by the thick oxide film 23 and another drain region 29 with the insulating layer 24 interposed therebetween, the field oxide transistor is considered to be a transistor having a very thick gate insulating film in construction. The thick oxide film 23 selectively formed is generally 2000 to 3000 .ANG. in thickness. Thus, when the field oxide transistor operates as a transistor, a threshold voltage V.sub.TH thereof is high such as 20 V, so that the field oxide transistor does not operate at normal operating voltage. In addition, the breakdown voltage of the gate insulating film 24 is high, so that the field oxide transistor is suitable for use in the input protective circuit.
However, as shown in FIG. 4, when a surge pulse caused by static electricity is inputted to the terminal 11, the transistor Q1 causes a punch-through phenomenon, so that the static electricity is discharged to a switching terminal. Referring to FIG. 4, the phenomenon is described.
When the surge pulse caused by positive static electricity is applied to the terminal 11, the potential of the source region is higher than that of the P type semiconductor substrate 28. Therefore, electrons in the P type semiconductor substrate 28 are attracted to the source region, so that all of the electrons are emitted, resulting in a depletion layer 27. When the potential of the source region is still higher than that of the P type semiconductor substrate 28, the depletion layer 27 extending from the source region expands and attains the drain region. At this time point, electrons in the drain region are attracted to the source region through the depletion layer 27, so that electrons rapidly flow. This means that current rapidly flows from the source region to the drain region, which is referred to as a punch-through phenomenon. The static pulse applied to the terminal 11 is discharged to a ground terminal, so that charges are not propagated to a transistor Q3. Therefore, the input protective circuit according to the illustrated structure serves as a circuit for protecting the transistor Q3.
Actually, the surge pulse caused by static electricity does not have a single mode but has a number of modes. The input protective circuit must be immune to any mode.
The surge pulse has modes as described in (a) to (c) below.
(a) discharge of a body charging model (body charging method) PA1 (b) discharge of an apparatus charging model (apparatus charging method) PA1 (c) discharge of a package charging model (package charging method)
The mode, in which static electricity charged in the human body is discharged to the device, is represented by an RC circuit shown in FIG. 8. In this mode, since static electricity is discharged to the device through a resistance of 1.5 K.OMEGA., a large current does not flow. However, large energy is consumed, so that thermal breakdown is liable to occur.
The mode, in which static electricity charged in a measuring instrument or the like is discharged to the device, is represented by an RC circuit shown in FIGS. 6 and 9. In this mode, since static electricity is discharged to the device not through resistance, a large current flows, so that dielectric breakdown is liable to occur and the current mode is liable to be broken down.
The mode, in which static electricity charged in a package itself of the device is discharged to the apparatus and the ground terminal through the device, is similar to discharge of the apparatus charging model as described in (b). Energy is smaller, as compared with discharge of the apparatus charging model as described in (b). However, the charging voltage has a higher value, as compared with the case (b), so that dielectric breakdown is liable to occur.
In the input protective circuit shown in FIG. 2, when the transistor Q1 is punched through, impedance from the input terminal 11 to the ground terminal is largely decreased, so that more current flows, as compared with discharge of the apparatus charging model as described in (b) and discharge by the package charging model as described in (c), and the transistor Q1 itself is broken down.
In order to prevent breakdown of the transistor Q1, the size of the transistor must be largely increased.